Tensilica Introduces Next-Generation 28 nm DSP IP Core

Tensilica®, Inc. today extended its Baseband Engine (BBE) family with the ConnX BBE64-128 -- the next-generation architecture for DSP (digital signal processor) IP (intellectual property) cores for SOC (system-on-chip) design.

The ConnX BBE64-128 provides over 100 GigaMACs performance in 28nm high-performance process technology, easily outperforming all other DSP IP cores on the market. The ConnX BBE64-128 was designed to meet the performance requirements for LTE (Long-Term Evolution) Advanced, which required at least five times more processing power than LTE.

Additionally, Tensilica introduced the ConnX BBE64-UE, which is specifically optimized for the low power and small area requirements of LTE Advanced handsets. These two new products are based on the new ConnX BBE64 architecture, which Tensilica's customers can use to optimize a DSP core for their particular requirements. Tensilica's product line also includes DSPs for LTE, including the popular ConnX BBE16 LTE DSP and the new ConnX SSP16, ConnX BSP3, and ConnX Turbo16, also introduced today.

"Tensilica has gained dominant market share in LTE by offering the broadest line of signal processing IP core options for LTE from micro DSPs to the ConnX BBE16," stated Eric Dewannain, Tensilica's vice president and general manager, Baseband Business Unit. "Now we are taking leadership with the world's fastest DSP IP core targeted for the upcoming LTE Advanced communications standard. Since all of our cores are based on the same foundation, they can be used as-is or optimized based on specific customer needs."

The ConnX BBE64-128 -- Breaking the 100 GigaMACs Barrier

The new ConnX BBE64-128 DSP can perform at 128 MACs per cycle for maximum throughput and minimum energy for most common MIMO (multiple in, multiple out) and channel estimation functions, used extensively in LTE Advanced software. It is based on a multislot VLIW (very long instruction word) architecture that provides high sustained performance across many applications with dense code and power efficiency. For non-vector algorithms, high code density can be achieved with modeless switching to Tensilica's smaller standard 16- and 24-bit instructions. Almost any operation can be performed from any slot in the VLIW format for greater sustained performance, lower energy and denser code.

This flexibility allowed Tensilica to design the BBE64-128 so it can run 128 MACs (multiply accumulates), which is particularly helpful for FIR (finite impulse response) filters and matrix operations that dominate LTE Advanced channel estimation and MIMO processing. "We leveraged our Tensilica DPU (dataplane processing unit) technology to create a more compact ConnX BBE64-128 DSP by providing the extra MACs just for those functions required by LTE Advanced when needed," stated Chris Rowen, Tensilica's CTO. "We believe this gives our customers the best performance, price and area efficiency."

Other features of the ConnX BBE64-128 that accelerate performance include:

• High-performance "soft bit" vector data types and operations including arbitrary field insertion and extraction for complex transmit operations, resulting in over 250 general 10-bit operations per cycle.
• Parallel register files for 10/20-bit and 40-bit data types for easier compilation and higher performance at lower power.
• Large register files for performance on complex code, reduced memory bandwidth requirements, reduced power and easier compilation.
• Single-cycle 16-way complex radix-4 and radix-8 FFT (fast Fourier transform) and DFT (discrete Fourier transform) for efficiency on arbitrary size transformations common to OFDM (orthogonal frequency-division multiplexing) algorithms.
• Accelerated interleaving for all bit, byte, half-word and word vector types for flexibility and efficiency in HARQ (hybrid automatic repeat request), forward error correction and convolutional coding.
• Cellular modem acceleration with an optimized capability for max-index search, demap, despread, vector divide, vector recip and square root.
• Rich operation resources -- multiple parallel execution units of each type to provide greater instruction scheduling flexibility and higher performance on code that uses one execution type heavily.
• Expanded vector memory operations for easier automatic compilation of complex C code at maximum performance on any data size and placement.
• A high-performance AXI interface for easy shared memory connection to memory and other cores.
• Extensibility -- the ability to optimize design for specific needs by adding custom instructions in minutes with Tensilica's automated tools -- allows great design flexibility for adding special memory interfaces, special per-SIMD (single instruction, multiple data) lane lookups or other required functions.
• The widest range of pre-defined "point-and-click" configuration options in Tensilica's history for maximum design flexibility.

Source: http://www.tensilica.com/