Taiwan-based Fabless ASIC and silicon IP provider Faraday Technology has chosen Aprisa physical design solution from US-based ATopTech specializing in providing physical design solutions.
Though 40 nm processes provide satisfaction to customers by showing high performance levels, low consumption of power and reduction in the cost of manufacturing, it has certain disadvantages such as variation in the process and high cross-talk effect. If these issues are not resolved properly, it could lead to a decline in quality and an unnecessary delay in closure of the design. ATopTech’s Aprisa which is also a netlist-to-GDSII physical implementation tool addresses these specific issues to provide enhanced routing performance and simultaneously achieve closure of design at optimal times.
Faraday Technology chose the Aprisa physical implementation tool after extensive and careful evaluation as the tool showed enhanced design performance, closure and tapeout for the 40 nm process. Aprisa carries out placement, optimisation, global and detailed routing, clock tree synthesis and place and route by using multi threading and distributed process technology. This helps the implementation tool to achieve consistent closure patterns and time and thus provide better overall design quality with faster turnaround time.
Other products in Faraday Technology’s silicon IP portfoilio are MPEG4, USB 2.0/3.0, Seriel ATA, DDRI/II/III, 10/100 ethernet, cell library, PCI Express and Memory compiler.