Cadence Design Systems, in collaboration with Samsung Electronics, has devised a methodology for 20-nm design that uses the latest technologies such as double patterning technology for internal test chips and joint customer implementation.
The new20-nm design methodology is designed for mobile consumer electronics applications to facilitate design at 20 nm and upcoming process nodes. Double patterning is a significant technology to lithography that provides higher routing density for sophisticated process nodes. Double patterning creates two masks for chip production by partitioning every metal layer of designs, thus providing smaller silicon area and higher metal density for 20-nm process node and below.
This advancement is the latest achievement in a multi-year partnership between Cadence and Samsung to design ICs at sophisticated process nodes. The Cadence Virtuoso custom/analog flow, Cadence signoff solutions, and Encounter RTL-to-GDSII flow were qualified for and implemented with Samsung’s 20-nm fabrication technology.
The Encounter Digital Implementation (EDI) System enabled an automated methodology to perform double patterning-correct placement and routing for the chip’s digital parts, utilizing its yet to be patented FlexColor technology to achieve real-time colorization. The EDI System provides DRC accuracy and die-area efficiency during placement, routing and optimization. The Cadence Encounter Power System, Encounter Timing System and QRC Extraction have been used for final signoff. QRC Extraction has been improved to accept manifold extraction values to handle difference in double-patterning alignment.
Cadence’s Senior Vice President of Research and Development for Silicon Realization Group, Dr. Chi-Ping Hsu stated that the company’s methodologies and tools for 20-nm design and Samsung’s production knowledge at advanced nodes have made this project a great success. The company expects many such technology advancements through its partnership with Samsung to facilitate customers at the 20-nm process node and below.