May 16 2014
Invarian, Inc., a provider of block-level to full-chip sign-off analysis EDA solutions, has developed advanced process node EM/IR tools that are certified for version 1.0 Design Rule Manual (DRM) of the TSMC 16nm FinFET process. Collaboration between TSMC and Invarian to support 16nm FinFET advanced designs with optimized tools ensures accurate, predictable and reliable silicon.
As the semiconductor industry transitions to FinFET technology, Invarian’s experience in electromigration and voltage-drop (EM/IR) can provide significant customer benefits. InVar can deliver physically accurate modeling results, including power, voltage, and signal. Invarian provides accuracy that correlates well with SPICE results. In addition, InVar passed the EM/IR certification using the ARM Cortex™ A15to validate needed flow integration. Invarian also provides direct iRCX support, so no intermediate or custom technology files are required.
The 16nm FinFET certification program with Invarian delivers:
- Analysis for 16nm FinFET DRM v1.0
- Complete coverage for DC/RMS/Peak EM rules
- Width-dependent Peak EM rules
- Complex Ipeak rules that require accurate Td modeling
- Supports all Power Grid rules
- Complete rule check support for both supply and signal nets
“Many customers, especially designing in mobile and networking markets where extremely complex SoC designs are the order of the day, are standardizing on 16nm FinFET designs for reducing leakage currents and boosting performance,” according to Jens Andersen, CEO of Invarian. “TSMC has a rigorous certification program and an aggressive effort to further Moore's Law. Invarian is pleased to be part of that effort by building a best-in-class silicon modeling solution to ensure that customers receive accurate, reliable and quality devices.”
“We welcome Invarian to our list of 16nm FinFET certified vendors,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “The extensive collaboration between Invarian and TSMC offers our customers the ability to perform Electromigration and Voltage-drop silicon modeling with confidence for advanced process technologies, including 16nm FinFET development.”