Atomic Layer Deposition for Nano & Macro-Electronics (ALD) for Nanoelectronics

Producing faster and more efficient microchips remains a constant challenge. The Atomic Layer Deposition for Nano & Macro-Electronics (ALD) process has been recognised by the International Technology Roadmap for Semiconductors (ITRS) as one of the core innovations to realise this goal in the long term. In collaboration with the University of Newcastle upon Tyne, CPI is bringing to the North East of England this key manufacturing process for producing silicon wafers and microsystems and will establish a new cleanroom specifically designed for R&D on advanced Atomic Layer Deposition for Nano & Macro-Electronics (ALD) materials. A range of Silicon – Germanium Atomic Layer Deposition for Nano & Macro-Electronics (ALD) R&D services will become available during mid 2007.

Atomic Layer Deposition for Nano & Macro-Electronics (ALD) and Its Advantages

Atomic Layer Deposition for Nano & Macro-Electronics (ALD) is the deposition of semiconductor material onto a silicon wafer to form a thin film that takes on the same crystal structure as the wafer. It is the superior electrical properties of the epitaxial films that improve the transistor's performance.

Advantages of Atomic Layer Deposition for Nano & Macro-Electronics (ALD) over Conventional Silicon Transistor Wireless Products

By controlling the material composition and lattice strain in different epitaxial layers, at the nanometre scale, it becomes possible to create novel electrical and optical properties in the semiconductor. One of the most notable commercial applications is the use of epitaxial alloys of Silicon (Si) and Germanium (Ge) in the hetero-junction bipolar transistor, which already provides improved performance over conventional Si transistor wireless products.

Other Applications for ALD SiGe Alloys

Other emerging uses of ALD SiGe alloys will integrate photonics devices on Si wafers such as waveguides, optical interconnects and light detectors or emitters, and in research on strained-Si layers for ultra-small Complementary Metal-Oxide Semiconductor (CMOS) devices for the next generation of microchips.

Atomic Layer Deposition for Nano & Macro-Electronics (ALD) Facilities Available at CPI

CPI has attracted two key research scientists from QinetiQ, Malvern - Dr. David Robbins and Dr. Yee Leong. Between them they bring over 40 years experience of Atomic Layer Deposition for Nano & Macro-Electronics (ALD) and device R&D to the region. CPI is presently relocating the Atomic Layer Deposition for Nano & Macro-Electronics (ALD) equipment from QinetiQ to the North East into a purpose built cleanroom in the School of Electrical, Electronic and Computer Engineering at the University of Newcastle upon Tyne.

It is anticipated that collaborative research between CPI and the University of Newcastle upon Tyne on ALD material for nanoelectronic devices will begin during 2006, with R&D services coming online during 2007.

This information has been sourced, reviewed and adapted from materials provided by CPI.

For more information on this source, please visit CPI.