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QuantumWise and DTU Collaborate to Model Electron-Phonon Coupling in Nanoelectronic Devices

The Danish company QuantumWise and the Technical University of Denmark (DTU) will engage in a project that makes it possible to simulate large-scale nano-electronic devices, where electron-phonon coupling is taken into account. The result will be an extension of the capabilities of the software package Atomistix ToolKit (ATK).

30 May 2013

Mentor’s Calibre nmPlatform for 16nm FinFET Receives TSMC Certification

Mentor Graphics Corp. today announced that its Calibre® physical verification platform has achieved version 0.1 of design reference manual (DRM) and SPICE model tool certification for TSMC’s 16nm manufacturing process, which incorporates 3D (FinFET) transistors for higher performance.

30 May 2013

Major Foundry Acquires Axcelis Purion M Medium Current Implanter for Sub 2Xnm Node Logic Devices

Axcelis Technologies, Inc. (Nasdaq: ACLS), a leading supplier of enabling ion implantation solutions for the semiconductor industry, announced today that it has shipped the Company's new Purion M™ medium current implanter to one of the world's leading foundries.

30 May 2013

Block Copolymer-Based PV Devices May Lead to New Class of Solar Energy Devices

A new version of solar cells created by laboratories at Rice and Pennsylvania State universities could open the door to research on a new class of solar energy devices.

30 May 2013

QMF and SPTS Achieve Epitaxial Growth of 3C SiC Films on 300mm Silicon Wafers

The Queensland Micro and Nanotechnology Facility (QMF) of Griffith University and industry partner SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, have announced epitaxial growth of 3C silicon carbide (SiC) films on 300mm silicon wafers.

30 May 2013

Mentor Graphics Partners with TSMC to Advance 20nm Physical Verification Kit

Mentor Graphics Corp. today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations. This joint effort has reduced Calibre® nmDRC™ 20nm signoff runtimes by at least a factor of 3X and memory requirements by 60% compared to initial design kits released last year.

30 May 2013

Semiconductor Packaging and Test Services Provider, STATS ChipPAC, Opens New Building in Singapore

STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company" ), a leading provider of advanced semiconductor packaging and test services, today celebrated the grand opening of its new building in Singapore with more than 150 distinguished guests, including Singapore Deputy Prime Minister and Coordinating Minister for National Security & Minister for Home Affairs, Mr. Teo Chee Hean, and other governmental and business representatives.

30 May 2013