Nanoelectronics News

RSS

UCLA Center for Function Accelerated nanoMaterial Engineering Awarded $5M to Advance Electronics

Five University of California, Riverside professors will receive a total of $5 million as part of a $35 million research center aimed at developing materials and structures that could enable more energy efficient computers, mobile phones, and other electronic devices.

From University of California at Riverside 5 Feb 2013

Cadence Partners with Common Platform Alliance to Showcase FinFET Design Technology

Cadence will showcase its joint development of advanced design technologies in partnership with the Common Platform Alliance (Samsung Electronics, IBM, and GLOBALFOUNDRIES) at the Common Platform Technology Forum on Feb. 5. Attendees can learn more about 20-nanometer and 14-nanometer FinFET standard cell and IP design, physical implementation, and extraction, timing and power signoff, as well as recent 14-nanometer tapeouts in which Cadence was involved.

From Cadence Design Systems 5 Feb 2013

Researchers Create 3D Microchip Using Nanotechnology

Scientists from the University of Cambridge have created, for the first time, a new type of microchip which allows information to travel in three dimensions. Currently, microchips can only pass digital information in a very limited way - from either left to right or front to back. The research was published today, 31 January, in Nature.

1 Feb 2013

Veeco’s NEXUS Physical Vapor Deposition System Receives Philips Qualification

Veeco Instruments Inc. announced today that Philips Innovation Services, a service provider within Royal Philips Electronics N.V., has recently qualified a NEXUS® Physical Vapor Deposition (PVD) System at its location on the High Tech Campus Eindhoven, Netherlands. This system will support Philips Innovation Services’ capabilities in a broad range of thin film device applications, including MEMS, sensors, nano-electronics and others.

From Veeco 31 Jan 2013

Researchers Test Nanometer-Scale Esaki Tunnel Diodes for Extending Battery Life

Researchers at Rochester Institute of Technology, international semiconductor consortium SEMATECH and Texas State University have demonstrated that use of new methods and materials for building integrated circuits can reduce power—extending battery life to 10 times longer for mobile applications compared to conventional transistors.

31 Jan 2013

Kilopass Completes JEDEC 3-Lot Qualification for SMIC LL CMOS Process Technologies

Kilopass Technology, Inc., the leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP), and Semiconductor Manufacturing International Corporation (NYSE: SMI) (SEHK: 981), a leading IC foundry, today announced that Kilopass IP has successfully completed the JEDEC 3-lot qualification for the SMIC 65nm, 55nm and 40nm low-leakage (LL) CMOS process technologies.

31 Jan 2013

SEMI and USPVMC Partner to Enhance Standards for Solar Thin Film Industry

SEMI and the U.S. Photovoltaic Manufacturing Consortium (PVMC) today announced the signing of a Memorandum of Understanding (MOU) to enhance their cooperation in areas of standards and roadmap activities for the solar thin film industry.

From College of Nanoscale Science and Engineering, University at Albany 30 Jan 2013

SWeNT to Display CNT Inks at Flexible Electronics and Displays Conference

SouthWest NanoTechnologies, Inc. (SWeNT®), the world leader in high quality, Single-Wall and Specialty Multi-Wall (SMW™) carbon nanotubes (CNT), will display its family of conductive and semi-conducting CNT inks for flexible printed electronics at the FlexTech Alliance 2013 Flexible Electronics and Displays Conference and Exhibition. SWeNT will be exhibiting in booth 48, Jan. 30th to Feb. 1st at the Phoenix Convention Center in Phoenix, AZ.

30 Jan 2013

TSMC OIP Forum 2012 Honors Berkeley Design Automation and Silicon Creations with Customers’ Choice Award

Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that its joint paper with Silicon Creations, “Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design,” presented at TSMC’s 2012 Open Innovation Platform® (OIP) Ecosystem Forum has received the TSMC OIP Forum 2012 Customers’ Choice Award.

30 Jan 2013

STATS ChipPAC and UMC Demonstrate TSV-Enabled 3D IC Chip Stacking Technology

STATS ChipPAC Ltd., a leading semiconductor advanced packaging and test service provider, and United Microelectronics Corporation ("UMC"), a leading global semiconductor foundry, today announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration.

From United Microelectronics Corporation 30 Jan 2013