Mentor Graphics Corporation (NASDAQ: MENT) today announced that it has expanded the set of Mentor tools and technologies included in TSMC Reference Flow 10.0. The expanded Mentor® track supports advanced functional verification for complex ICs, netlist-to-GDSII implementation for 28nm ICs, tighter integration with the ubiquitous Calibre® physical verification and DFM platform, and tools for layout aware test failure diagnosis. In addition, this newly introduced Mentor track also addresses low power design with Mentor tools for functional verification, IC implementation and IC testing.
“Mentor Graphics continues to expand its Reference Flow offerings to cover the total IC design cycle from the systems level through functional verification, place-and-route, physical verification and silicon test, as well as offering new solutions such as low power, manufacturing variability, and silicon yield analysis,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.
The Reference Flow 10.0 Mentor track provides new capabilities in many areas, including the first Mentor implementation solution in TSMC Reference Flow, the Olympus-SoC™ place-and-route system. For advanced IC implementation, the Olympus-SoC system has new features addressing on-chip variation, 28nm routing and low power design:
- Advanced stage-based OCV analysis and optimization – Setting different stage-based OCV values helps reduce pessimism and enables faster design closure.
- N28 routing rules – Provides 28nm support for the complete netlist-to-GDSII flow, including support for the 28nm transparent half-node.
- Disjoint power domain – Supports multiple floor plans in the same voltage domain to minimize congestion and reduce the need for hierarchy changes.
- UPF hierarchical low power automation – Provides both top-down and bottom-up support for UPF-based, low-power designs giving designers greater flexibility.
Design-for-Manufacturing capabilities within the Olympus-SoC and Calibre platforms have been expanded and more tightly integrated to address manufacturing variability issues at 28nm and beyond:
- Litho hotspot fixing – Improves yield by enabling the Olympus-SoC place-and-route tool to automatically fix litho hotspots detected by the Calibre LFD™ tool.
- Quick convergence of DMx fill for timing and ECOs – The Olympus-SoC system invokes the Calibre CMPAnalyzer tool (which works with TSMC’s VCMP simulator) to analyze thickness variation for its impact on timing. The Olympus-SoC tool also supports hierarchical, incremental and timing-driven metal fill flows, significantly improving yield and reducing pessimism.
- Cell-index-aware placement – Reduces congestion and speeds routing by allotting more room for cells with difficult pin access.
- Electrical DFM – The Calibre xRC™ and Calibre CMPAnalyzer products are integrated to allow simulated thickness information to be incorporated into parasitic extraction results to drive accurate circuit simulation. This also provides a solution for more efficient corner simulation and statistical analysis by providing statistical parasitic information to the Mentor Eldo® circuit simulator.
In addition, the Calibre nmDRC and Calibre nmLVS products support signoff physical verification of 2D and 3D system in package (SIP) designs in Reference Flow 10.0.
Reference Flow 10.0 includes new features in the TestKompress® and YieldAssist™ products for better fault detection, power-aware testing and failure diagnosis:
- Embedded multiple detect ATPG – Increases bridge fault detection without any increase in pattern size or test time.
- Layout aware diagnosis – Eliminates false bridge/open suspects, enhances diagnosis resolution, and builds a foundation for effective yield analysis.
- Low-power ATPG – Reduces power during all phases of scan test utilizing a constant-fill decompressor and power-aware control of existing clock gates.
Reference Flow 10.0 also includes advanced functional verification features from the Questa® and 0-In® platforms for improved validation of complex IC designs.
- Standards-based solution featuring support for IEEE Std. 1801-2009™ UPF and IEEE Std. 1800-2005™ SystemVerilog.
- Integrated low-power simulation and formal capabilities that verify advanced power management circuitry early in the design flow.
- Static and dynamic verification of complex clock domain crossing circuits to ensure proper operation in standard and low power modes.
“The complete Mentor design-to-silicon track in TSMC’s Reference Flow 10.0 allows us to address our mutual customers’ biggest challenges for 28nm, including low power design and verification, large-scale SoC implementation, manufacturing variability, and cost-effective test and yield analysis,” said Walden C. Rhines, chairman and CEO, Mentor Graphics. “The industry transition to 28nm processes also presents new technical challenges, which Mentor is in a unique position to solve. Our close collaboration with TSMC allows us to close the loop between designers and foundries with tools that help our customers get their products to market faster with higher performance and greater reliability.”