Feb 18 2010
Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, and Virage Logic (Nasdaq: VIRL), the semiconductor industry's trusted IP partner, today announced a partnership agreement to provide customers with comprehensive design solutions including access to Virage Logic's extensive Physical and advanced Interface intellectual property (IP) portfolio.
In particular, as more and more customers develop energy efficient devices, Virage Logic's low power IP combined with Open-Silicon's lower power design technology enable the development of significantly lower power silicon.
"This partnership underscores our continued commitment to meet our customers' needs for lower power, managed variability, and faster time-to-market," said Dr. Naveed Sherwani, CEO and president of Open-Silicon. "We selected Virage Logic as our trusted IP partner because of their proven track record in providing a broad portfolio of highly differentiated IP. This offering, paired with Open-Silicon's OpenMODEL™ proven integration capability, allows customers to achieve very high levels of performance while reducing overall system power."
The partnership presents a well-aligned technology offering. Virage Logic, a leader in low power semiconductor IP technology, uses several advanced power management features within the SiWare™ Memory compilers and SiWare™ Logic libraries that enable customers to dramatically reduce leakage current while maximizing performance. Open-Silicon's VariMAX back biasing technology similarly works with Virage Logic's tapless SiWare Logic standard cell libraries to reduce leakage for the IC's logic. By changing the amount of bias used on individual chips, VariMAX effectively tunes the silicon for optimum power and thereby boosts production yields. This latest collaboration builds on a recently announced co-developed test chip with working silicon running at 1.1GHz that was achieved using Open-Silicon's patented CoreMAX™ performance enhancement technology and Virage Logic's advanced SiWare Memory compilers.
"As power management and efficiency are becoming increasingly critical in a multiplicity of products and technologies, our collaboration with Open-Silicon underscores how we are working with our design ecosystem partners to help SoC designers address these challenges," said Dr. Alex Shubat, president and CEO of Virage Logic. "Open-Silicon's MAX Technologies working in conjunction with Virage Logic's extensive semiconductor IP portfolio enables our mutual customers to address a broad range of SoC design requirements."
The SiWare product line, first introduced in October 2007 for the 65-nanometer(nm) process and now in use by more than 20 customers on the 40nm process, has been proven to address the increasingly complex design requirements that are placed on physical IP at advanced processes. The power-optimized memories for advanced processes minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.
All SiWare Memory compilers are fully supported by Virage Logic's STAR™ Memory System, the company's flagship embedded memory test and repair system that may be used with Virage Logic memories as well as with other commercially available or internally developed memories. For repair purposes, the STAR Memory System deploys foundry-developed eFuse for repair signature storage. The STAR Memory System employs test algorithms tailored for advanced processes for higher product reliability and accelerated time-to-yield.
The SiWare Logic product line includes yield-optimized standard cells for a wide variety of design applications at 40nm with multiple threshold process variants. SiWare Logic libraries offer three separate architectures to optimize circuits for Ultra-High-Density, High-Speed, or general use. SiWare Logic Ultra-Low-Power extension libraries also provide designers with the most advanced power management capabilities.
Source: http://www.open-silicon.com/