Soitec, a manufacturer of innovative semiconductor materials for the energy and electronics industries, has revealed that its planar fully depleted silicon on insulator (FD-SOI) technology has been selected by ST-Ericsson for upcoming mobile platforms.
The fully depleted transistors are built upon Soitec's novel substrates comprising an ultrathin top layer, which plays a major role in deciding the key features of the transistor. Soitec’s FD-SOI wafers improve the performance of NovaThor and lower battery usage by reducing up to 35% of power consumption.
Soitec’s Chief Operating Officer, Paul Boudre stated that FD offers a minimum-risk option for semiconductor firms like ST-Ericsson that are looking to benefit from a fully depleted transistor design, while leveraging current design and production capabilities.
The Assistant General Manager for Technology R&D at STMicroelectronics, Joël Hartmann commented that the company together with IBM, Soitec and Leti has spent several years in the development of FD-SOI technology and the company has recently shown the low-power and high-performance advantages of this technology over traditional bulk CMOS on many IPs at ≤28 nm. These features make the FD-SOI technology specifically suitable for tablet and wireless applications by offering FinFET’s fully depleted transistor benefits on a planar conventional technology and also allowing sophisticated back bias techniques that are not offered by FinFETs.
Since semiconductor companies are forced to migrate beyond 28 nm process nodes due to innovative form factors, it is evident that the conventional bulk CMOS process technology is not able to balance these features efficiently. FD wafers allow a planar, fully depleted transistor design that leverages semiconductor manufacturers to eliminate the bulk CMOS bottlenecks by making the efficient design of future-generation, low-power processors for mobile computing devices and smartphones. This design is critical in deploying a transistor technology that is capable of solving the variability, leakage and scaling issues related with CMOS technology beginning at 28 nm, with minimal process complexity.