Synopsys, a company offering intellectual property, software, and services utilized in the design, production and verification of electronic systems and components, has partnered with TSMC and Altera to deliver silicon-validate modeling of important parasitic effects in StarRC solution, developed by Synopsys, for TSMC’s 28-nm process nodes.
The StarRC solution met the rigorous model-to-silicon accuracy standards of TSMC's 28-nm process technology to facilitate superior-performance designs at the sophisticated nodes. Altera has implemented the StarRC solution to obtain accurate extraction of signoffs and to speed up market-reach time for its 28-nm FPGA designs.
StarRC provides silicon-accurate modeling for the latest 28-nm process effects as qualified by customers and foundries on their taped-out designs. The solution’s important 28-nm features are area-dependent via capacitance and resistance; modeling of augmented width difference of conductors caused by larger via shapes’ via-faceting and coupling effects, optical-proximity-correction and sophisticated retargeting effects; and improved parasitic extraction of layout-dependent device. Moreover, StarRC features the Rapid3D field solver technology for rapid, high-accuracy three-dimensional extraction validated by TSMC for the process technology at 28 nm.
Altera’s Director of CAD engineering, Eugene Chen stated that the company’s 28-nm partnership showed that StarRC can fulfill the stringent performance and accuracy standards of Altera for tool selection to offer superior-quality products to customers. StarRC is now completely implemented as the signoff parasitic extraction solution for most of the sophisticated 28-nm Stratix V FPGA devices being manufactured by the company.
TSMC’s Senior Director of Design Infrastructure Marketing, Suk Lee commented that the company is happy to see that its mutual customers, like Altera, have understood the advantages of this partnership and implemented the solution to get a high accuracy on their advanced 28-nm designs.