Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that HiSilicon Technologies, a leading provider of communication network and digital media chipset solutions, has signed an agreement to significantly expand its use of the Cadence® digital and custom/analog flows for 16 nanometer FinFET designs, and to collaborate on the design flow for 10 nanometer and 7 nanometer nodes.
HiSilicon has also broadly adopted Cadence digital and custom/analog verification solutions, and has licensed Cadence DDR IP and the Cadence 3D-IC solution to deploy multiple heterogeneous dies in a single package on a silicon interposer substrate.
The selection of Cadence tools and IP follows HiSilicon's successful design of the industry's first production 16 nanometer FinFET system-on-chip (SoC). Employing 32 processor cores and a 64-bit architecture, the SoC is a network processor running at speeds up to 2.6 GHz, and was designed using Cadence digital, custom, 3D-IC, verification and emulation tools and DDR4 IP.
For the digital flow, the agreement includes access to Cadence Encounter® Digital Implementation System, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, and Quantus™ QRC Extraction Solution. For custom/analog design, HiSilicon designers are using Cadence Virtuoso® custom design platform, Spectre® simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor. The agreement also includes an increase in licenses of Incisive® Enterprise Simulator for advanced verification.
For 3D-IC designs, HiSilicon is utilizing the Cadence 3D-IC solution, which includes Encounter Digital Implementation System and Allegro® tools for IC/package co-design, and Voltus and Sigrity™ solutions for power, thermal and signal integrity verification.
"To continue providing highly differentiated communications and digital media chipset solutions, HiSilicon relies on partners like Cadence to provide implementation and verification solutions that enable high-quality silicon optimized for performance, power and area," said Lin Yu (Colbert), senior director of Platform & Key Technologies Development Department at HiSilicon Technologies. "HiSilicon and Cadence have a long history of close collaboration and ongoing design success. Based on this success we are increasing our use of the Cadence solutions, and look forward to developing innovative new chipset solutions employing 16 nanometer technology, as well as 10 and 7 nanometer nodes in the future."
"Cadence is focused on developing long-lasting partnerships with leading-edge companies like HiSilicon to deliver innovative and groundbreaking devices and systems," said Charlie Huang, executive vice president, Worldwide Field Operations and System & Verification Group at Cadence. "This agreement with HiSilicon builds on years of collaboration, and we look forward to our expanded relationship on new advanced networking solutions."