Building on many years of close collaboration and numerous joint research programs, STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, and the French Institute of Materials, Microelectronics and Nanosciences in Provence (IM2NP - CNRS / Aix-Marseille University / University of Toulon / ISEN engineering school), member of the Carnot STAR (Science and Technology for Research Applications) Institute, have announced the official launch of a new joint research laboratory to develop the next generations of high-reliability, ultra-miniaturized electronic components.
Visual REER
The Radiation Effects and Electrical Reliability (REER) Joint Laboratory is a multi-site research establishment that will bring together teams from the IM2NP Institute, based in Marseille and Toulon, and specialist engineers from the ST facility in Crolles, near Grenoble.
The REER Joint Laboratory's science program will focus on two main areas of research: the effect of radiation on digital nanometer-scale circuits and the electrical reliability of nanometer-scale CMOS (complementary metal-oxide semiconductor) technologies. These lines of research are crucially important for ST and its ability to produce integrated circuits with extremely high levels of reliability for a wide range of key sectors, such as the automotive sector, networks, medical, space and security.
For these types of applications, the intrinsic constraints of electronic components (electrical fields, mechanical stress, temperature, etc.) and some environmental constraints (especially particle radiation from natural or artificial sources) are becoming an increasingly critical issue for current and future generations of integrated circuits.
Consequently, they need to be accurately characterized, modelled and simulated in order to predict and mitigate their effects, which is one of the key objectives of the new joint research facility.
In addition, a host of challenges and hurdles need to be overcome in the development of future nanoelectronic technologies, and these must be better understood at all stages of the integration process. The joint laboratory's research will range from the most fundamental aspects of phenomena at the atomic level to systems, materials, the physics of devices and the design of robust circuits.
Its work will be conducted in a globally competitive environment and will focus on the most advanced microelectronic technologies, such as the 28-nanometer technology node and beyond, in particular the FD-SOI (fully depleted silicon-on-insulator) industrial cluster developed by ST at its Crolles site. This key process technology is enabling ST to spearhead development of the most innovative world-class nanoelectronic circuits.
Recently opened, the joint laboratory is already involved in numerous collaborative programs and projects at the national, European and international level, in conjunction with the European CATRENE cluster, the ENIAC initiative and support programs led by the French General Directorate for Enterprises (DGE) and the French defense procurement agency (DGA). In the next five years, the lab will offer placements for a number of high-level doctoral students, mostly in the context of public-private partnership research supported by the French government's CIFRE scheme (industrial agreement for training through research).