Nanofabrication News

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Juniper Networks Improves TAT for 28nm IP Implementation for Networking Applications with Cadence Innovus

Cadence Design Systems, Inc. today announced that Juniper Networks has utilized Cadence® Innovus™ Implementation System to improve turnaround time (TAT) for physical implementation of their most complex 28-nanometer (nm) intellectual property (IP) for networking applications. The networking company was able to achieve throughput of more than 1.8 million cells per day while also improving out-of-the-box design performance by 15 percent.

From Cadence Design Systems 12 Mar 2015

Uniquify Selected by Nufront as DDR IP Provider for 28nm SoC Project

Uniquify, a leading high-performance semiconductor intellectual property (IP) and system-on-chip (SoC) integration and manufacturing services supplier, today announced an agreement with Nufront of Beijing, China, to provide a high-performance DDR subsystem IP solution that supports DDR4, DDR3, LPDDR3 and LPDDR2 protocols.

12 Mar 2015

Major OSAT Manufacturer Selects Rudolph JetStep® Advanced Packaging Lithography System for Evaluation

Rudolph Technologies, Inc. announced today that a major outsourced assembly and test (OSAT) manufacturer has selected the JetStep® Advanced Packaging Lithography System for evaluation. The tool, which ships this week, will be used to develop copper (Cu) pillar bumping and through silicon via (TSV) processes used in the development of next-generation flip chip technology.

From Onto Innovation 12 Mar 2015

Freescale® Achieves 7X Turnaround Time Gain on Multiple 28nm Designs with Cadence® Innovus™ Implementation System

Cadence Design Systems, Inc. today announced that Freescale® Semiconductor has achieved a 7X gain in turnaround time with Cadence® Innovus™ Implementation System over its previous production environment while maintaining its quality of results.

From Cadence Design Systems 12 Mar 2015

Building Blocks for Creation of Nano-Knots

As sailors and mountaineers know very well, every knot carries out a specific function. There's a knot that slides, one that "floats", and one that comes undone with a single pull. In the field of nanotechnology as well, it is useful to have several kinds of molecular knots to be used, for instance, as mechanically resistant nano-cages for delivering chemical compounds or for confining and controlling toxic reagents.

11 Mar 2015

MaxLinear Utilizes Cadence® Innovus™ Implementation System on Multi-Million Instance 28nm Chip

Cadence Design Systems, Inc. today announced that MaxLinear, Inc. used the Cadence® Innovus™ Implementation System on a multi-million instance 28 nanometer chip, significantly improving both area and turnaround time.

From Cadence Design Systems 11 Mar 2015

CEA-Leti Launches Silicon Impulse IC Design Competence Center

CEA-Leti today announced the launch of its Silicon Impulse IC design competence center, a comprehensive IC technology platform offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles.

From CEA-Leti 11 Mar 2015

HiSilicon Technologies Deploys Synopsys Platform for FinFET Designs Targeting TSMC's 16nm Technology

Synopsys, Inc. today announced that HiSilicon Technologies, a leading provider for telecom network, wireless terminal and digital media chipset solutions, has broadly deployed Synopsys' Galaxy™ Design Platform for the implementation of ARM® Cortex®-A72, Cortex -A57 and Cortex -A53 processor-based FinFET designs targeting TSMC's 16-nanometer (nm) process technology.

From Synopsys, Inc. 11 Mar 2015

Cadence Innovus Implementation System Supports Advanced 16/14/10nm FinFET

Cadence Design Systems, Inc. today unveiled Cadence® Innovus™ Implementation System, its next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class power, performance and area (PPA) while accelerating time to market.

From Cadence Design Systems 11 Mar 2015

Toshiba Successfully Tapes Out Advanced 40nm SoC with Synopsys IC Compiler II

Synopsys, Inc. today announced that its IC Compiler™ II place and route solution has enabled Toshiba to accelerate tapeout of an advanced 40-nanometer (nm) system on chip (SoC). The impressive speed-up and superior QoR delivered by IC Compiler II enabled Toshiba to achieve higher designer productivity and better device performance.

From Synopsys, Inc. 10 Mar 2015

Nanofabrication News

Juniper Networks Improves TAT for 28nm IP Implementation for Networking Applications with Cadence Innovus

Uniquify Selected by Nufront as DDR IP Provider for 28nm SoC Project

Major OSAT Manufacturer Selects Rudolph JetStep® Advanced Packaging Lithography System for Evaluation

Freescale® Achieves 7X Turnaround Time Gain on Multiple 28nm Designs with Cadence® Innovus™ Implementation System

Building Blocks for Creation of Nano-Knots

MaxLinear Utilizes Cadence® Innovus™ Implementation System on Multi-Million Instance 28nm Chip

CEA-Leti Launches Silicon Impulse IC Design Competence Center

HiSilicon Technologies Deploys Synopsys Platform for FinFET Designs Targeting TSMC's 16nm Technology

Cadence Innovus Implementation System Supports Advanced 16/14/10nm FinFET

Toshiba Successfully Tapes Out Advanced 40nm SoC with Synopsys IC Compiler II

Biochar-Modified Titanium Dioxide Nanocomposites for Enhanced Water Treatment

Boosting Hydrogen Fuel Production with TiO2 and Copper-Based MOFs

New Nanocage Material Removes Up to 90% of Toxic PFAS from Water

Enhancing Chitosan Films with Silanized Hexagonal Boron Nitride for Sustainable Applications

N-Doped Ti3O5: Enhanced Photocatalytic Removal of Phenolic Compounds from Wastewater

Overcoming Nanogold Production Challenges

Electrospinning and the Future of Nanotechnology

How Electrospinning is Shaping the Future of Nanotechnology

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