Ultratech, a leading supplier of lithography and laser-processing systems used to manufacture semiconductor devices and high-brightness LEDs (HB-LEDs), today introduced its new in-line wafer inspection system, the Superfast 3G, which provides the flexibility to address a wide range of applications including improved overlay control and enhanced yield.
STMicroelectronics, Soitec (Euronext) and CMP (Circuits Multi Projets®) today announced that ST's CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process, which uses innovative silicon substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. ST is releasing this process technology to third parties as it nears completion of its first commercial wafers.
Nano-ribbons of silicon configured so the atoms resemble chicken wire could hold the key to ultrahigh density data storage and information processing systems of the future.
The College of Nanoscale Science and Engineering (CNSE) of the University at Albany announced today that its Smart System Technology and Commercialization Center of Excellence (STC) in Rochester has received the critical and prestigious designation as a Trusted Foundry – Aggregator by the U.S. Department of Defense’s (DoD) Defense Microelectronics Agency.
Case Western Reserve University researchers have won a $1.2 million grant to develop technology for mass-producing flexible electronic devices at a whole new level of small.
Berkeley Design Automation, provider of the world’s fastest nanometer circuit verification, today announced that TSMC has incorporated the Analog FastSPICE Platform in its Custom Design Reference Flow for 20nm Device Noise Analysis and Circuit-Specific Process Corners.
Cadence Design Systems, a leader in global electronic design innovation, announced today that TSMC has selected Cadence® solutions for its 20-nanometer design infrastructure. The solutions cover the Virtuoso® custom/analog and Encounter® RTL-to-signoff platforms.
As further demonstration of Governor Andrew Cuomo's nanotechnology-driven innovation economy and its success at attracting global corporations, M+W Group (M+W) announced today that it has been selected by the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, United States, associate member for facilities and infrastructure for the Global 450mm Consortium (G450C), where M+W will spearhead development of new facility and infrastructure technologies and manage building and facility suppliers selected to participate in the G450C program.
SpringSoft, and Mentor Graphics® Corporation today announced that the Laker™-Calibre® RealTime custom layout flow with signoff-quality design rule checking (DRC) in real time is selected for the TSMC Custom Design Reference Flow. The Reference Flow addresses 20-nanometer (nm) chip design and verification complexity.
Synopsys, a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced 20-nanometer (nm) process technology support for the TSMC 20nm Reference flow. This includes Synopsys® Galaxy™ Implementation Platform support for the latest TSMC 20nm design rules and models.
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