Jan 26 2010
Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), and Solido Design Automation, provider of Variation Designer, today announced a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level. Driven by demand by a leading fabless semiconductor provider, the companies have proven a solution in which Variation Designer utilizes the AFS Platform. The result is variation analysis capabilities that enable designers to rapidly reduce variation risk.
The Analog FastSPICE Platform (AFS Platform) is the industry’s only unified circuit verification platform for analog, mixed-signal, and RF design. It always delivers true SPICE accurate results, while providing 5x-20x higher performance than traditional SPICE, >10 million-element capacity, and the industry’s only comprehensive device noise analysis. The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. The AFS Platform includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Co-Simulation, AFS Transient Noise Analysis, and AFS RF Analysis.
"Rapidly eliminating yield losses due to process variation in nanometer analog, mixed-signal, and RF designs is a key requirement for high-volume nanometer ICs,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “The excellent results from the proven Solido Variation Designer integration with the Berkeley Design Automation AFS Platform will provide our mutual customers a dramatic increase in productivity and design turn-around-time.”
Variation Designer, along with Solido’s PVT (process, voltage, temperature) Corner, Statistical, and Proximity applications packages can be deployed for transistor level design to account for global, local, environmental and proximity related variation effects. The benefit of these solutions is improved designs and reduced variation risk in less time. Variation Designer is used across the transistor level design cycle – from PVT corner simulations to statistical analysis – to determine mismatch effects or yield.
"Variation Designer provides a scalable and extensible solution for solving problems created by process variation in nanometer designs at the transistor level,” said Amit Gupta, president and CEO of Solido Design Automation. “When using the AFS Platform as the simulation engine in Variation Designer, we are able to deliver a fast variation analysis and fix capability. Our mutual customers will directly benefit from the performance improvement of the combined flow."