Apr 20 2010
Presto Engineering Inc., a pioneer of the labless business model for bringing semiconductor products into volume production, and CEA-Leti today announced that they have begun a three-year collaboration to develop test and analysis capability for 3D semiconductor devices.
The project, a common lab that will include Presto’s new R&D center at CEA-Leti, will focus on extending the company’s test, reliability and failure analysis solutions to through-silicon vias (TSVs), the interconnects between levels on 3D devices.
“IDMs and fabless companies are increasingly outsourcing critical test and analysis functions. The adoption of 3D technologies will fuel this trend and product engineering will require new skills, reliable processes and specialized equipment,” said Michel Villemain, CEO of Presto Engineering. “CEA-Leti has industry-leading expertise in 3D integration, advanced interconnects and TSVs, and by working side by side with CEA-Leti’s experts, Presto will build on our proven product engineering capabilities for the arrival of TSVs.”
Presto’s R&D program with CEA-Leti is focused on:
- Characterization of TSVs reliability, defect susceptibility and electrical performance aspects
- Identifying existing test protocols that are appropriate for 3D structures while developing new ones to meet new challenges, and
- Bringing up new diagnostic methods or tools to identify root cause of failures
The common lab will make the ATE and debug process as well as the product engineering platform available for third parties.
“This partnership with Presto is a natural complement to CEA-Leti’s many 3D integration projects and joint labs,” said Laurent Malier, CEO of CEA-Leti. “We will identify the key challenges of 3D product engineering, so semiconductor manufacturers will have reliable, state-of-the-art test and analysis options when they are ready to go to market with 3D devices that feature TSVs.”
In addition to its broad goals, the joint lab will enable Presto to develop critical test and analysis techniques, such as probing specific areas of TSVs without affecting the device itself.
“Testing 3D-IC prototypes will require detecting, recognizing and understanding the failure modes, and mechanisms through their electrical signature,” said Cédric Mayor, R&D director for Presto Engineering Europe, a subsidiary of Presto Engineering Inc. “Faulty TSVs may have many root causes that have to be investigated and catalogued in such a way that our ultimate test program and diagnostic tool detect them efficiently.”
Presto, which recently opened a hub in Caen, France, offers enhanced RF and 3D-integration expertise and advanced test, reliability, fault-isolation and failure-analysis services. Its Design Success Analysis™ offering includes first-silicon validation, as well as characterization of new processes, new designs, and process transfers.