Jul 14 2010
The Soitec Group (Euronext Paris), the world's leading supplier of engineered substrates for the microelectronics industry, announced today that the company is ready with the Ultra-Thin Buried Oxide (UTBOX) extension to its Ultra-Thin (UT) silicon-on-insulator (SOI) platform, thereby providing a robust substrate solution for chip designers tackling the performance, power and density challenges of mobile consumer devices.
Fully Depleted (FD) planar body transistors are now recognized as the right path on the CMOS roadmap for the 22nm generation and beyond. With FD planar transistor technology on UTBOX wafers, chip designers can enhance their usual design flows and techniques. High-volume capacity is available for the 22nm node at Soitec's manufacturing sites in France and Singapore.
"Soitec is ready with the UTBOX wafers for planar FD architectures: the infrastructure, the process maturity, yield and the capacity are all in place to support demand," said Soitec president and chairman, Andre-Jacques Auberton-Herve. "Industry leaders confirm that FD planar technology is the right choice for mobile consumer products, which need higher performance without compromising power. Our UTBOX offering shows the critical role our materials play as the starting point for energy-efficient, state-of-the-art electronics."
With an ultra-thin, insulating buried oxide layer, system-on-chip (SOC) designers and system architects can leverage standard techniques for attaining lower power and higher performance as needed by the target applications. The UTBOX option further complements the existing advantages of planar FD technology, which solves transistor variability issues, delivers the best device electrostatics, and enables SRAM to operate at lower supply voltages (Vdd). It is an evolutionary and highly manufacturable technology that offers simple processes and continuity of design tools, leading to a very cost-effective solution.
For FD planar to live up to its tremendous promise, the starting wafers must meet very stringent top silicon uniformity specifications. With ultra-thin top silicon thickness variation within a +/- 0.5nm maximum range, and a buried oxide layer as thin as 10nm, these wafers are in full compliance with customer requirements.
"FD SOI is the right technology at the right time. As the challenges to control bulk leakages become very expensive and unreliable, FD SOI offers a simple solution. Additionally, the fact that FD SOI is a planar and scalable technology with no history effects provides a seamless design transition. This is a powerful combination," said Horacio Mendez, executive director of the SOI Industry Consortium.
Soitec will exhibit in booth # 1333 in Moscone Convention Center's South Hall at the Semicon West trade show, July 13-15 in San Francisco.
Source: http://www.soitec.com/