Oct 20 2010
Extreme DA™, the leader in new-generation timing analysis software, announced the 2010.09 release of its GoldTime™ product with 2X faster timing analysis, including signal integrity (SI) effects and enhanced features over its 2009 release.
GoldTime continues to provide the fastest way to analyze complex digital designs with the smallest number of computer resources. The accuracy and completeness of timing analysis is essential to the success of digital designs that will become working integrated circuits (ICs).
Full-chip Timing Analysis
The latest semiconductor processes with their nanometer-scale geometries allow the creation of extremely dense and complex designs. Signal interference is very likely to occur in complex designs and must be analyzed prior to chip manufacture. GoldTime from Extreme DA can analyze delay and glitch propagation effects that can cause timing errors and make ICs fail in production. Variations in the latest nanometer IC processes make statistical timing analysis also an analysis requirement, so designs will be have a high yield in production. Extreme’s unique ThreadWave™ technology tackles this computing challenge head-on and handles the largest digital designs with virtually unlimited capacity. In the 2010.09 GoldTime release additional enhancements include 25% faster incremental timing analysis and 2X faster restore of analysis sessions.
Mustafa Celik, CEO of Extreme DA, said, “In the last twelve months we have been able to again increase the speed of analysis in GoldTime by 2X. Other solutions sacrifice accuracy and quality of analysis to achieve faster runtimes. We continue to be the market leader in delivering SPICE-correlated timing analysis that combines the fastest speed and smallest memory footprint.”
Customer Success
Celik continued, “Our growing customer base means we have over 1,500 licenses in production use around the world. We just closed another multi-year agreement with a top fabless semiconductor company after demonstrating 3X faster performance than their legacy tool, saving them 7 to 10 days of development time for designs implemented in a sub-32nm process. We look forward to aiding other design teams who need new-generation SI and Parametric-OCV statistical timing analysis.”
Source: http://www.extreme-da.com/