Novel Repair Scheme Helps Improve Yields of Wafer-Level 3D-ICs

MonolithIC 3D has developed a yield repair scheme capable of improving yields of 3D-ICs built with multiple wafers stacked over each other.

The Silicon Valley-based startup company also claims that its novel technology can be used to build high-yield products that have die-sizes close to wafer sizes. The ultra-scale integration scheme uses a repair layer comprising uncommitted devices over an apex layer, which can be tailored later in the production process to repair bottom layers utilizing a direct-write e-beam tool. Defects can be rectified by substituting them with repair logic generated instantaneously in the repair layer.

This fine-grained repair scheme eliminates performance penalty and has very low power, because the faulty logic is merely a few microns below the replacement logic cone. It is capable of significantly increasing both yield and integration. It eliminates design overhead and has minimal cost penalties.

According to Zvi Or-Bach, MonolithIC 3D’s President and Chief Executive Officer, the company’s monolithic three-dimensional technology together with an economical repair strategy built upon the direct-write e-beam technology allows remarkably high orders of integration. He added that this drastically decreases power, paving the way to develop future-generation of products ranging from mobile electronics to supercomputers.

MonolithIC 3D’s Chief Software Architect, Ze’ev Wurman stated that as scaling advancing to sub-20 nm process nodes, many producers are facing low-yield issues and are seeking for schemes to obtain powerful high-yield products with high numbers of less powerful components. The company’s scheme is an ideal solution to this issue, Wurman concluded.