Electronic Design Automation (EDA) solutions provider, Synopsys has developed a suite of solutions comprising placing, routing, physical verification and signoff capabilities to support designing of System-on-Chip (SoC) for 20 nm node.
Synopsys 20 nm solution
This is the result of collaborative work between Synopsys and Samsung Electronics and would facilitate engineers to carry out design and development at the 20 nm process geometry at Samsung. The first delivery from the collaboration was the 20-nm chip that operated on Samsung’s High-k metal gate process technology.
The main constraints to 20 nm process are the double-patterning requirement and the complications in design arising out of Design Rule Checking (DRC). The new solution addresses these limitations by providing a single stop-shop for 20 nm design. The suite of Synopsys tools from the Galaxy Implementation Platform for 20 nm node comprises an IC compiler for double-patterning aware placement, routing and extraction, an IC validator for accelerated design closure, quick detection of yield detractor patterns and DPT decomposition violations along with automatic repair, PrimeTime timing signoff tool, and StarRC extraction tool.
Dr. Antun Domic, Senior VP and GM of the Implementation Group at Synopsys and Dr. Kyu-Myung Choi, Senior VP for Device Solutions at Samsung Electronics, stated the benefits of combining Samsung's 20 nm process technology with Synopsys’ Galaxy Implementation Platform for their mutual customers by way of less power and less circuit area consumption and quicker time-to-market.