DAC 2015: Open-Silicon to Demonstrate ASIC Solutions

Open-Silicon, an ASIC solutions provider, today announced it will demonstrate the company's Industrial IoT ASIC Platform, 28Gbps SerDes Evaluation Platform, 2.5D SoC Solution and HMC 2.0 Memory Controller IP at DAC (Jun 8-11, 2015- San Francisco, CA). Open-Silicon is also presenting several posters on "Advance ASIC Solutions" on Low Power Methodology, Connectivity Verification, Validation and High Speed SerDes Integration.

What: Exhibit Booth: Open-Silicon will showcase the company's

1. Industrial IoT ASIC Platform- This demonstrates end-to-end communication between sensor hubs and cloud platform through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. The Industrial IoT system setup is a part of Open-Silicon's Spec2Chip IoT Platform, which allows IoT ASIC designs to be evaluated at system level.
2. 28G SerDes Evaluation Platform- This evaluation platform for ASIC development will enable the rapid deployment of chips and systems for high bandwidth networks. The platform includes a full board with packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.
3. 2.5D SoC Solution- This platform demonstrates a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded two dual core 1GHz ARM Cortex™-A9 ARM processors, connected across a 2.5D silicon interposer.
4. HMC 2.0 Memory Controller ASIC IP- This IP demo will showcase a platform based on Xilinx Virtex-7 XC7VX690T FPGA that includes a fully validated design that integrates HMC controller along with HMC exerciser functions. The demo platform allows quick evaluation of the HMC technology and performance testing of the HMC links.

When: June 8th to 10th10 A.M to 7 P.M
Where: Exhibit Floor, Booth # 615, Moscone Center, San Francisco, CA

Poster Presentations:

Open-Silicon will also underscore the company's growing expertise in developing and delivering advanced ASIC solutions on Low Power Methodology, Connectivity Verification, Validation and High Speed SerDes integration.

1. Case Study: Low-Power Methodology Achieves Power Requirements for Camera SoC Without Losing Performance
   Speaker: Devendra V. Godbole - Technical Lead, Front End Design
2. Connectivity Model Approach for Connectivity Verification
   Speaker: Mrugesh Walimbe - Architect, Front End Design
3. Hardware Random Transaction Generator for Validation
   Speaker: Mrugesh Walimbe - Architect, Front End Design
4. Optimized ASIC Design Integrating 28Gbps SerDes
   Speakers: Naveen H N, Sr. Design Manager & Abu Eghan, Sr. Packaging Manager

When: June 9th 4:30 P.M to 6 P.M
Where: Design and IP Track Poster Session, Exhibit Floor, Moscone Center, San Francisco, CA