Aug 25 2015
Top technologists from AMD are detailing the engineering accomplishments behind the performance and energy efficiency of the new high-performance Accelerated Processing Unit (APU), codenamed "Carrizo," and the new AMD Radeon™ R9 Fury family of GPUs, codenamed "Fiji," at the prestigious annual Hot Chips symposium starting today.
The presentations will focus on new details of the high-definition video and graphics processing engines on the 6th Generation AMD A-Series APU ("Carrizo"), and the eight year journey leading to die-stacking technology and all-new memory architecture included on the latest top-of-the-line AMD Radeon™ Fury Series GPUs ("Fiji") for 4K gaming and VR. Using a true System-on-Chip (SoC) design, 6th Generation AMD A-Series processors are designed to reduce the power consumed by the x86 cores alone by 40 percent,1 while providing substantial gains in CPU, graphics, and multimedia performance versus the prior generation APU. The new AMD Radeon™ R9 Fury X GPU achieves up to 1.5x the performance-per-watt of the previous high-end GPU from AMD.2
"With our new generation of APU and GPU technology, our engineering teams left no stone unturned for performance and energy efficiency," said Mark Papermaster, chief technology officer at AMD. "Using innovative design for our APUs, we've vastly increased the number of transistors on-chip to increase functionality and performance, implemented advanced power management, and completed the hardware implementation of Heterogeneous System Architecture. For our latest GPUs, AMD is the first to introduce breakthrough technology in the form of die-stacking and High-Bandwidth Memory. The results are great products with very large generational performance-per-watt gains."
The details will be shared in two symposium presentations. On August 24, Guhan Krishnan, AMD fellow, design engineering, will present "Energy efficiency in graphics and multimedia in 28nm 'Carrizo' APU." This session will provide an in-depth view of the multitude of advancements resulting in superior performance, battery life, and user experiences on performance notebook and convertible form factors. In "AMD's next Generation GPU and memory architecture" on August 25, Joe Macri, corporate vice president and product chief technology officer at AMD, will share the journey from inception to market that covered eight years and involved several key partners, as well as provide architectural details behind the performance and efficiency of the new AMD Radeon R9 Fury line of GPUs.
Die-Stacking Journey Culminates In High-End GPU
The path to the new "Fiji" family of AMD Radeon R9 Fury GPUs began with exploring the best die-stacking option for bringing large amounts of memory into the same chip package with the GPU while dramatically increasing the memory bandwidth available to a high-performance graphics engine, without increasing power consumption. Working with memory partner SK Hynix, the new GPUs based on AMD Graphics Core Next (GCN) architecture offer up to 4 GB of high-bandwidth memory (HBM) over a 4096-bit interface to achieve an unprecedented 512 Gb/s memory bandwidth. The new memory is stacked close to the GPU in the package by implementing the first high-volume interposer as well as the first through-silicon vias (TSVs) and micro-bumps in the graphics industry. HBM and the interposer provide 60 percent more bandwidth than previous generation GDDR5 memory3 and 4x the performance-per-watt of GDDR5.4 At the same time, the "Fiji" family is capable of up to 8.6 TFLOPS performance, a nearly 35 percent increase over the previous generation (Radeon™ R9 290 Series GPUs).The result is an improvement of up to 1.5x performance-per-watt.
APU Energy Efficiency
The new 6th Generation AMD A-Series APU harnesses up to 12 compute cores (4 CPU + 8 GPU) leveraging AMD "Excavator" CPU cores and the third generation of AMD GCN architecture. The result is a groundbreaking processor that boasts more than twice the battery life of its predecessor5 and up to 2x faster gaming performance than competitive processors.6 The processor incorporates a number of genuine power management firsts for AMD, including the first implementation of Adaptive Voltage and Frequency Scaling (AVFS), the first High Efficiency Video Compression (HEVC)/H.265 decoder on-chip for notebook, and the first APU to utilize color compression and bandwidth-saving technologies. In addition, AMD will share details on clock and power gating management, disclosures on the new integrated Southbridge, and improvements in entering sleep and idle modes. AMD will also discuss numerous additional efficiency improvements, including the enhanced ability to quickly put the SoC in the lowest power state and self-refresh DRAM.
Combined, the AMD energy efficiency innovations on its 6th Generation A-Series APUs are designed to deliver power savings roughly on the order of a manufacturing technology shrink while staying in a well-characterized, cost-optimized 28nm manufacturing process.