Panasonic and Renesas Technology Collaborating on Development of SoCs at 32-nm Process Node

Building on the successful partnership on their joint process technology development since 1998, Panasonic Corporation and Renesas Technology Corp. are now collaborating on the development of elemental process technologies for systems-on-a-chip (SoCs) of the next-generation 32-nm node. The two companies are confident that their 32-nm node transistor technology and other advances can soon be applied to products in mass production.

It is anticipated that SoCs at the 32-nm node will deliver lower cost and improved performance enabled by miniaturization of their design rules, yet there are many technical issues that need to be solved. In particular, it is necessary to introduce new materials and develop new technologies to break through barriers to further integration, such as transistor gate leakage and inconsistent electrical characteristic problems, which are often found in existing technologies. Introducing new materials is technically difficult; however, the technology challenges in achieving acceptable transistor performance at the 32-nm node are more formidable than they were at previous-generation process nodes.

To meet these challenges, the new 32-nm SoC process employs a newly developed transistor technology with a metal/high-k¹ gate stack structure and interconnect technology, using a new ultra-low-k² material. To achieve a device using complementary metal-insulator semiconductor (CMIS)³ technology, a type of complementary Metal Oxide Semiconductor (CMOS), at a 32-nm node, an ultrathin film cap layer⁴ is applied at the atomic level to transistors with a metal/high-k gate stack structure under optimized conditions. This enables development of a conventional transistor configuration, which allows the use of an oxidized silicon film as the gate insulation layer. The introduction of the cap layer has been shown to improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors, thereby enabling the operation of large-scale circuits.

The two partners have been working on the joint development of next-generation SoC technology, even before the establishment of Renesas Technology. Their joint development work has yielded impressive results until now. They developed a 130-nm DRAM composite process in 2001, a 90-nm SoC process in 2002, a 90-nm DRAM composite process in 2004, a 65-nm SoC process in 2005, and a 45-nm SoC process in 2007.

The latest development on the new 32-nm fabrication process will be applied to SoCs for advanced mobile and digital home appliance products.

Building on their accumulated technology expertise and resulted new advances, as well as their successful partnership of many years, Panasonic and Renesas Technology hope to continue efficiently developing the advanced process technology that can be quickly moved to mass production respectively.

Notes:

1. Metal/high-k: A type of field effect transistor in which the gate terminals and gate insulator layers have a stacked configuration, and in which the gate terminals are made of metal and the gate insulator layers are made of a high-k material. One commonly used high-k material is hafnium.
2. Ultra-low-k: A material with extremely low permittivity, even in comparison with other low-permittivity materials used as wiring insulation.
3. CMIS: A type of complementary field effect transistor in which the gate terminals are separated electrically by an insulating film. In a CMOS transistor, the CMIS gate insulator layers are made of oxidized silicon.
4. Ultrathin film cap layer: An ultrathin layer introduced to adjust the threshold value of the transistor. This contributes to improved transistor reliability and helps suppress inconsistent electrical characteristics.