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GLOBALFOUNDRIES Supports Agilent's GoldenGate and Momentum Simulators for 65-nm RF CMOS Process

GLOBALFOUNDRIES has declared support for Agilent Technologies' Momentum 3D planar electromagnetic (EM) and GoldenGate RFIC circuit simulators for GLOBALFOUNDRIES’ 65-nm low power enhanced (LPe) RF CMOS process.

6 Jun 2012

TSMC Qualifies Cadence Physical Verification System for 28 nm and 20 nm Processes

Cadence Design Systems has reported that the Cadence Physical Verification System (PVS) has been qualified by TSMC for 28-nm design signoff. In addition, TSMC has also concluded Phase I certification of Cadence PVS for its 20-nm process.

6 Jun 2012

Tiempo Announces Availability of First 32 nm Fully Clockless Circuit

Tiempo together with STMicroelectronics has designed a first-of-its-kind 32-nm fully clockless circuit, which was produced as a first-time-right silicon chip.

4 Jun 2012

World's First Liquid Phase Photoelectron Spectroscopy Machine to be Unveiled at the University of Nottingham

X-ray Photoelectron Spectroscopy (XPS) machines currently allow the study of only solid substances. In what is touted as a breakthrough that would facilitate atomistic measurements of liquid surfaces, the University of Nottingham has announced that it is all set to unveil the world’s first Liquid Phase Photoelectron Spectroscopy (LiPPS) machine at its Nottingham Nanotechnology and Nanoscience Centre (NNNC).

2 Jun 2012

GLOBALFOUNDRIES to Demonstrate 28 nm AMS Design Flow at Design Automation Conference

GLOBALFOUNDRIES plans to display an improved silicon-validated design flow for the company’s 28 nm super low power (SLP) Gate First High-k Metal Gate process technology at the Design Automation Conference to be held in San Francisco, California.

2 Jun 2012

TSMC’s 20 nm Phase I Certification for Synopsys Design Implementation Tools

Synopsys has reported that Synopsys design implementation tools has earned Phase I Certification from TSMC for its 20-nm process.

2 Jun 2012

STMicroelectronics Used Cadence Tools for 20-nm Test Chip Tapeout

Cadence Design Systems has reported that STMicroelectronics has used Cadence tools to tape out a 20-nm test chip, integrating customized analog and digital technologies to facilitate mixed-signal SoC design at 20 nm process node.

2 Jun 2012

Linköping University Researchers Develop Integrated Chemical Chip

Klas Tybrandt, a Linköping University student pursuing PhD in organic electronics, has devised an integrated chemical chip. The study findings have been reported in the Nature Communications journal.

30 May 2012

TSMC and Renesas Extend MCU Partnership to 40 nm eFlash Process Technology

TSMC and Renesas Electronics have extended their partnership on microcontroller (MCU) technology to 40 nm embedded flash (eFlash) process technology to produce MCU products for advanced consumer and automotive applications.

29 May 2012

Tanner EDA Adds Analog FastSPICE with Nanometer SPICE Accuracy to its Design Suite

Tanner EDA’s full-flow HiPer Silicon design suite is now offered along with Berkley Design Inc.’s Analog FastSPICE platform. The HiPer silicon suite offers software solutions for circuit design ranging from drafting schematic layouts to physical circuit layout and verification.

28 May 2012