Feb 22 2013
ARM and Synopsys, Inc. today announced a collaboration to optimize performance of ARM® Mali™ graphics processing units (GPUs) in 20-nanometer (nm) and smaller process geometries using the Synopsys Galaxy™ Implementation Platform.
The companies successfully taped out the first ARM Mali-T658 design using a 20nm process technology, ARM Artisan® physical IP and shader functionality. The resulting RTL-through-sign-off design flow includes double-patterning support throughout. The ongoing collaboration will help designers optimize the implementation of Mali GPUs for their target applications.
"Mali GPUs are found in most Android™ tablets and smart digital TVs currently shipping, and are one of the most popular graphics solutions for smartphones. Users' demand for advanced graphics continues to increase, which means that optimizing GPUs for selected end devices is essential," said Pete Hutton , general manager, Media Processing Division, ARM. "Building on a long history of successful collaborations with Synopsys, this implementation will enable designers to optimally implement ARM Mali-T600 family GPUs using Synopsys tools in sub 20nm leading-edge process technologies."
The Mali-T600 series includes five members (Mali-T604, Mali-T624, Mali-T628, Mali-T658 and Mali-T678), which have all been designed to provide exceptional graphics performance and they feature the first graphics technology to bring GPU compute functionality into mobile devices. This combined functionality brings additional hardware complexity which is further compounded by the new double-patterning requirements introduced by 20nm and below technologies.
Smaller process technologies, such as 20nm and below, require a highly integrated design flow for fast closure while delivering optimal results. The collaboration used the Galaxy Implementation Platform to produce a methodology tuned for the Mali GPU with ARM Artisan physical IP in 20nm. Primary tools used included Synopsys' Design Compiler® synthesis, Formality® formal verification, DFTMAX™ and TetraMAX® test, IC Compiler™ layout, StarRC™ extraction and PrimeTime® timing analysis and signoff. In addition, IC Validator In-Design capabilities for physical verification were used during the implementation process to speed design closure. The methodology also benefitted from the use of DC Explorer & Dataflow Analyzer to perform early exploration, especially of floorplans and macro placement so critical to GPU performance.
"Twenty-nanometer and smaller process technologies introduce new complexity requiring early and deep technical collaboration among semiconductor ecosystem partners," said Antun Domic , senior vice president and general manager, Implementation Group, Synopsys. "Through this collaboration with ARM, the Synopsys Galaxy Implementation Platform with In-Design physical verification combines with the ARM Mali IP and Artisan physical IP to provide a proven, DPT-compliant solution that will help accelerate the time to design closure on complex SoCs at 20 nanometers and below."