Algo-Logic Systems Introduces 3rd Generation TCP Endpoint with Nanosecond Ultra-Low-Latency

Algo-Logic Systems, a recognized leader in providing hardware-accelerated, deterministic, ultra-low-latency products, systems and solutions for accelerated finance, packet processing and embedded system industries, today announced availability of their new 3rd Generation TCP Endpoint.

The IP-Core enables FPGA-implemented logic to directly communicate over 10 Gigabit Ethernet networks with remote hardware or software devices and includes a robust hardware application programming interface that supports multiple real-world accelerated finance use cases.

The mature, proven, reliable and network-tested TCP endpoint delivers ultra-low-latency of 76-nanoseconds with the highest possible TCP bandwidth at full duplex rates of 20 Gbps scalable to 40/100 Gbps. Circuits have been implemented on both Altera and Xilinx FPGA devices and are compatible for deployment with all widely deployed FPGA platforms including Terasic DE5Net, Solarflare AOE and NetFPGA 10G. Plans are underway to also certify the IP-Core on additional end-customer platforms, including the Bittware S5PH-Q and Nallatech P385 platforms. The key TCP Endpoint features include:

• 8, 16, 32 TCP Sessions per instance with user-defined MAC, Port, & IP Addresses
• Small Logic Footprint: 6.7% ALMs for 32 TCP sessions in Stratix V A7 for each TOE
• High Throughput: Can send and receive small and large payloads including jumbo frames
• Full 10GE Line Rate (20 Gbps Duplex) in an architecture that scales to support 40GE & 100GE
• Low latency proxy model that allows true parallel processing of client and exchange traffic communicating with a single application session in FPGA logic
• OS independent GUI or UDP network API for control and configuration

Algo-Logic’s U.S.-exchange-certified TCP Endpoint hardware delivers deterministic, 76-nanosecond low-latency performance when used along with streaming applications implemented in FPGA logic. The Algo-Logic TCP Endpoint seamlessly runs at the full Ethernet line-rate of 156.25 MHz enabling the core to run synchronously with the MAC and processing logic. Moreover, the TCP Endpoint can be seamlessly integrated with all other components of Algo-Logic’s Low Latency Application Library, including pre-built protocol parsing libraries, market data filtering, market data distribution, feed normalization and protocol translation solutions; as well as with customer applications including pre-trade risk-checks, order books, associative lookup engines, and data acquisition to achieve fastest time-to-market FPGA application deployments. The TCP Endpoint configurations are specifically designed for real-world accelerated finance use-cases and commercial deployment scenarios that include:

• Standard TCP Endpoint with single TOE instance for communication between FPGA hardware and remote hardware or software endpoint with up to 32 simultaneous sessions.
• Proxy Model for up to 32 application session between 64 TCP endpoints
• Multiple dedicated TCP Endpoints on multiple physical interfaces supporting up to 14 hosts each with 32 sessions
• Multiple proxy model TCP Endpoints for Aggregated Traffic to multiple Physical Interfaces on multiple links (supporting up to 448 TCP sessions)

Algo-Logic's world-class hardware accelerated systems and solutions are used by banks, trading firms, hedge-funds, exchanges and financial institutions to accelerate their network processing for Risk-Checks (sec 15c 3-5), protocol parsing, symbol filtering, order book processing, order injection, proprietary trading strategies, high frequency trading, financial surveillance systems, and algorithmic trading.