New 3D Chip Incorporates Data Storage and Computing

As embedded intelligence is gradually moving into more and more areas of day-to-day life, fields spanning from personalized medicine to autonomous driving are producing massive quantities of data. But just as the overflow of data is touching huge proportions, the ability of computer chips to process it into valuable information is stalling.

Currently, Researchers at MIT and Stanford University have constructed a new chip to overcome this obstacle. The results have been published in the journal Nature, by Lead Author Max Shulaker, an Assistant Professor of Electrical Engineering and Computer Science at MIT. Shulaker started the research as a PhD Student together with H.S. Philip Wong and his Advisor Subhasish Mitra, Professors of Electrical Engineering and Computer Science at Stanford. The team also included Professors Krishna Saraswat and Roger Howe also from Stanford.

Computers these days contain a variety of chips cobbled together. One chip is used for computing and another for data storage, and the connections between the two are restricted. As applications examine increasingly huge volumes of data, the limited rate at which data can be transferred between different chips is posing a serious communication “bottleneck.” And with minimal real estate on the chip, there is not sufficient room to position them side-by-side, even as they have been miniaturized (an occurrence known as Moore’s Law).

To further complicate things, the underlying devices, the silicon transistors are no longer advancing at the historic rate that they have been for years.

The new prototype chip is a radical modification from present chips. It uses many nanotechnologies, along with a new computer architecture, to reverse these two trends.

Rather than depending on silicon-based devices, the chip employs carbon nanotubes, which are 2D graphene sheets formed into nanocylinders, and resistive random-access memory (RRAM) cells, a type of non-volatile memory that functions by altering the resistance of a solid dielectric material. The research team combined more than one million RRAM cells and two million carbon nanotube field-effect transistors, creating the most intricate nanoelectronic system ever made using emerging nanotechnologies.

The RRAM and carbon nanotubes are constructed vertically overlapping one another, making a new, dense 3D computer architecture with interleaving layers of memory and logic. By inserting ultra-dense wires between these layers, this 3D architecture has the potential to sort the communication bottleneck.

However, such an architecture is not imaginable with current silicon-based technology, according to the paper’s Lead Author, Max Shulaker, who is a chief member of MIT’s Microsystems Technology Laboratories. “Circuits today are 2D, since building conventional silicon transistors involves extremely high temperatures of over 1,000 degrees Celsius,” says Shulaker. “If you then build a second layer of silicon circuits on top, that high temperature will damage the bottom layer of circuits.”

The main point in this research is that RRAM memory and carbon nanotube circuits can be fabricated at much lower temperatures, lower than 200 °C. “This means they can be built up in layers without harming the circuits beneath,” Shulaker says.

This provides a number of concurrent benefits for future computing systems.

The devices are better: Logic made from carbon nanotubes can be an order of magnitude more energy-efficient compared to today’s logic made from silicon, and similarly, RRAM can be denser, faster, and more energy-efficient compared to DRAM.

Philip Wong, Professor of Electrical Engineering and Computer Science, Stanford

“In addition to improved devices, 3D integration can address another key consideration in systems: the interconnects within and between chips,” Saraswat adds.

“The new 3D computer architecture provides dense and fine-grained integration of computating and data storage, drastically overcoming the bottleneck from moving data between chips,” Mitra says. “As a result, the chip is able to store massive amounts of data and perform on-chip processing to transform a data deluge into useful information.”

To show the technology’s potential, the team took advantage of the ability of carbon nanotubes to also serve as sensors. On the top layer of the chip they positioned more than one million carbon nanotube-based sensors, which they used to detect and categorize ambient gases.

Because of the layering of data storage, sensing and computing, the chip was capable of measuring each of the sensors in parallel, and then write directly into its memory, producing massive bandwidth, Shulaker says.

Three-dimensional integration is the most promising approach to pursue the technology scaling path proposed by Moore’s laws, allowing a growing number of devices to be incorporated per unit volume, according to Jan Rabaey, a Professor of Electrical Engineering and Computer Science at the University of California at Berkeley, who was not part of the research.

It leads to a fundamentally different perspective on computing architectures, enabling an intimate interweaving of memory and logic. These structures may be particularly suited for alternative learning-based computational paradigms such as brain-inspired systems and deep neural nets, and the approach presented by the authors is definitely a great first step in that direction.

Jan Rabaey, a Professor of Electrical Engineering and Computer Science, University of California at Berkeley

“One big advantage of our demonstration is that it is compatible with today’s silicon infrastructure, both in terms of fabrication and design,” says Howe.

“The fact that this strategy is both CMOS [complementary metal-oxide-semiconductor] compatible and viable for a variety of applications suggests that it is a significant step in the continued advancement of Moore’s Law,” says Ken Hansen, President and CEO of the Semiconductor Research Corporation, which supported the research. “To sustain the promise of Moore’s Law economics, innovative heterogeneous approaches are required as dimensional scaling is no longer sufficient. This pioneering work embodies that philosophy.”

The team is keen on enhancing the underlying nanotechnologies, while examining the new 3D computer architecture. For Shulaker, the following step is working with Massachusetts-based semiconductor company Analog Devices to create new versions of the system that exploit its ability to perform data processing and sensing on the same chip.

So, for example, the devices could be used to spot signs of disease by sensing specific compounds in the breath of a patient, says Shulaker.

The technology could not only improve traditional computing, but it also opens up a whole new range of applications that we can target. My students are now investigating how we can produce chips that do more than just computing.

Max Shulaker, Lead Author and Chief Member of MIT’s Microsystems Technology Laboratories

“This demonstration of the 3D integration of sensors, memory, and logic is an exceptionally innovative development that leverages current CMOS technology with the new capabilities of carbon nanotube field–effect transistors,” says Sam Fuller, CTO emeritus of Analog Devices, who was not involved in the research. “This has the potential to be the platform for many revolutionary applications in the future.”

This research was funded by the Defense Advanced Research Projects Agency, the National Science Foundation, Semiconductor Research Corporation, STARnet SONIC, and member companies of the Stanford SystemX Alliance.