Oct 17 2012
SpringSoft, and Mentor Graphics® Corporation today announced that the Laker™-Calibre® RealTime custom layout flow with signoff-quality design rule checking (DRC) in real time is selected for the TSMC Custom Design Reference Flow. The Reference Flow addresses 20-nanometer (nm) chip design and verification complexity.
The latest Laker-Calibre RealTime flow integrates SpringSoft’s next-generation Laker3™ OA custom IC design platform with the Mentor Graphics Calibre RealTime platform and golden rule decks used for foundry signoff. It provides signoff-quality physical verification during 20nm layout creation with advanced voltage-dependent and double-patterning design rule checking features. Deployment of this capability in the TSMC 20nm Custom Design Reference Flow enables designers to reach design closure faster and shorten overall design cycles.
Laker-Calibre RealTime Flow
Continuous feedback is necessary to comply with design rules at 20nm. For 20nm designs, engineers must meet new voltage-dependent design rules. In the Laker-Calibre RealTime flow, the Calibre DRC engine continuously monitors the design layout creation in the Laker environment and instantly flags design rule violations. For example, voltages are automatically annotated onto the layout figures as they are created, so any of TSMC’s new voltage-dependent DRC (VDRC) violations will be flagged at the moment they occur. This flow leverages the Si2 OpenAccess (OA) database and runtime model (RTM) with the TSMC Interoperable Process Design Kit (iPDK) to address 20nm layout challenges with a multi-vendor solution that operates like a single tool.
According to Joseph Davis, Mentor Graphics director of product marketing, Calibre User Interface and Integration, “The OpenAccess-based integration of Calibre RealTime with the Laker custom design platform provides a way for custom IC designers to maintain their productivity. Designers can focus on optimizing their circuits with the confidence that the design is being constantly checked against the foundry-provided golden signoff rules, including voltage-dependent rules, as they work. Designers also get immediate, accurate and succinct guidance on how to fix any violations that occur.”
“This integration with Calibre gives Laker customers access to signoff-quality 20nm design rule checking in real time and complements the built-in design rule-driven layout features of Laker,” said Dave Reed, senior director of marketing for custom IC design solutions at SpringSoft. “Our work with Mentor Graphics combines the most widely used interoperable custom design platform with signoff-quality, real-time DRC and is now fully supported in TSMC’s 20nm flows. This demonstrates the power of interoperable solutions for meeting 20nm design challenges.”
“Mentor Graphics and SpringSoft validate the vision and success of TSMC’s Open Innovation Platform®. Their collaborative approach to design enablement at advanced nodes underscores their commitment to meeting the needs of chip designers,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division