Oct 28 2015
Synopsys, Inc. today announced that its IC Compiler™ II place and route system has been successfully deployed on more than 100 production designs in the first year since its introduction in 2014.
This usage includes more than 50 unique customers across 18 different foundry process nodes. This game-changing successor to IC Compiler, the industry's leading place and route solution, has enabled first-pass silicon success on dozens of these production designs ranging from 130 nanometer (nm) to the latest 10-nm process node. Throughout its broad, real-world usage, IC Compiler II has consistently demonstrated a ten-fold improvement in throughput while achieving even higher quality of results (QoR). Industry leaders pursuing advanced applications have successfully deployed this new place and route system on IP (intellectual property) blocks at the chip level, while others have completed multiple tapeouts. Many have even chosen to displace incumbent third-party solutions. Coming so soon after the launch in 2014, this level of successful deployment serves as a resounding endorsement of the game-changing nature of IC Compiler II.
"Cavium is already reaping the benefits of IC Compiler II, through both completed tapeouts and others in flight," said Vishnu Yalala, senior director of IC Engineering at Cavium. "With data volumes increasing exponentially year-over-year, we see IC Compiler II as a truly exciting solution to help meet our ever-shrinking development schedules for our highly differentiated networking solutions across all process nodes. Given the very real benefits that we have seen since our early collaboration with Synopsys, we are aggressively deploying and standardizing on IC Compiler II across our extensive development program."
IC Compiler II is Synopsys' state-of-the-art, production-ready place and route system designed from the ground up to deliver the highest productivity and best QoR for designs across all process nodes. Architected around a modern, low-memory footprint and natively multi-threaded infrastructure, IC Compiler II is able to handle designs comprising more than 500 million placeable instances hierarchically, and has proven capacity for over 10-million instance block implementation. Comprised of an optimized, place and route-focused data model, coupled with an extensible library system offering unique, geographically separated development capabilities, IC Compiler II eases user adoption by utilizing industry-standard input and output formats, as well as familiar interfaces and process technology files. Additionally, IC Compiler II brings industry-leading, ultra-high-capacity automated design planning, unique clock-building technology and patented global analytical optimization that result in a highly convergent design implementation flow. Together, these technologies enable enhanced QoR across all key power, performance and area implementation metrics as well as accelerate that all important time-to-market goal. The culmination of numerous years of engineering innovation, these industry-first technologies enable IC Compiler II to deliver 5X faster runtime along within half the memory footprint while requiring half the iterations required to achieve the same target QoR – ultimately resulting in a 10X boost in design throughput and designer productivity.
"IC Compiler II is a game-changing product, enabling a world of opportunities for our customers," said Antun Domic, executive vice president and general manager at Synopsys. "During the course of the past year, we have seen broad and rapidly growing adoption across the industry, leading to a full pipeline of production designs across the process spectrum. We are continuing to work closely with customers and our foundry and ecosystem partners to broadly accelerate products to market with the power of 10X."