Feb 1 2010
Calypto® Design Systems Inc., the leader in sequential analysis technology, today announced that Virage Logic's 45-nanometer (nm) and 28nm SiWare™ Memory compilers now automatically generate PowerPro® MG power optimization models for reducing System-on-Chip (SoC) embedded memory power. This support is the result of a close, ongoing collaboration between the two companies to dramatically reduce on-chip SoC memory power. Using PowerPro MG, designers can reduce both dynamic and leakage memory power, resulting in up to 80 percent memory power reduction compared to previous implementations.
“We are working with Calypto to maximize the opportunity for on-chip memory power savings and enable designers to very easily take advantage of the low-power modes offered by Virage Logic's industry-leading SiWare Memory compilers,” said Brani Buric, executive vice president, marketing and sales, of Virage Logic. “The combination of PowerPro MG and our SiWare Memory products allows us to deliver a fully automated, world-class solution to our customers, enabling them to produce the most power-efficient designs possible in the most advanced process nodes available.”
Virage Logic delivers memory compilers that enable SoC designers to explore the tradeoffs between performance, area, power and statistical yield to generate optimal memory configurations. The latest release of the 45nm and 28nm SiWare Memory compliers will now automatically generate PowerPro MG models. This enables design teams to easily integrate PowerPro MG into their fully automated design flows to reduce both dynamic and leakage memory power.
“Power remains the number one SoC design consideration today and on-chip memory power can account for up to 70 percent of the power consumed in an SoC,” said Tom Sandoval, chief executive officer of Calypto. “The automatic creation of the PowerPro MG memory model by Virage Logic's SiWare Memory compilers is a great example of how innovative companies are working together to solve some of the most difficult problems SoC designers face.”
Using Calypto's patented sequential analysis technology, PowerPro MG constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible. PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic. PowerPro MG reduces dynamic power by automatically generating logic that controls the memory enable signal and eliminates unnecessary memory accesses. PowerPro MG reduces leakage power by automatically generating logic that controls the sleep modes of individual embedded memories.